1. Field of the Invention
The invention relates to a method of detecting an integrated circuit in failure among a plurality of integrated circuits, and more particularly to a method of doing so, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit.
The invention relates also to an apparatus for detecting an integrated circuit in failure among a plurality of integrated circuits, and more particularly to an apparatus for doing so, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit.
The invention relates further to a recording medium readable by a computer, storing a program therein for causing a computer to either carry out the above-mentioned method or act as the above-mentioned apparatus.
2. Description of the Related Art
A method of detecting an integrated circuit in failure among integrated circuits has usually been carried out in order to detect and remove integrated circuits which are not capable of performing desired operations due to defectiveness in fabrication steps, and ship only integrated circuits which can properly operate.
For instance, the inventor had suggested a method of detecting an integrated circuit in failure in Proceedings of the 1998 IEICE General Conference C-12-8 xe2x80x9cDiagnosis of failure in an integrated circuit by analysis of a current with power spectrumxe2x80x9d. In this method, a current running through an integrated circuit while the integrated circuit is in operation is analyzed with respect to a frequency, to thereby detect an abnormal current caused by defectiveness in fabrication steps.
Japanese Unexamined Patent Publication No. 9-33604 has suggested a method of identifying a failure mode, comprising the steps of detecting a logic operation test pattern in which a power source current abnormally runs through CMOS logic circuit, which is one of internal circuits of an integrated circuit, in an amount greater than a predetermined amount while the CMOS logic circuit stops its logic operation, when a logic operation test pattern is input into the CMOS logic circuit through an input terminal thereof, extracting a characteristic between a power source voltage and a power source current with the detected logic operation test pattern being input into the CMOS logic circuit, and comparing the thus extracted characteristic between a power source voltage and a power source current to similarity between a failure mode and data between a power source voltage and a power source current, stored in a database, to thereby identify a failure mode occurring in the CMOS logic circuit.
Japanese Unexamined Patent Publication No. 9-211088 has suggested a method of detecting a failure in CMOS integrated circuit by observing a static power source current independent of switching of a transistor, among a current running through CMOS integrated circuit when a test pattern is applied to CMOS integrated circuit. The suggested method is carried out in an apparatus including means for repeatedly applying a test pattern to CMOS integrated circuit under test, means for measuring a power source current supplied to CMOS integrated circuit under test, and means for measuring power spectrum of the detected power source current. The method includes the step of judging whether CMOS integrated circuit is in failure or not by observing a magnitude of power having a predetermined frequency band, among the power spectrum of the power source current.
Japanese Unexamined Patent Publication No. 10-301843 has suggested a data processor comprising a main memory including a plurality of memories, and a plurality of processors transmitting a plurality of requests of data transfer to the main memory for each unit of data, and processing data transmitted from the main memory. The plurality of memories include means for detecting bank competition which occurs by the requests transmitted from the processors, and transmit a bank competition signal to the processors, and a circuit measuring a period of time during which bank competition occurs, based on the bank competition signal.
Japanese Unexamined Patent Publication No. 11-2663 has suggested a method of detecting a failure in CMOS integrated circuit by observing a static power source current running CMOS integrated circuit when a series of test patterns is repeatedly applied to CMOS integrated circuit from LSI tester. The method includes the steps of repeatedly applying test patterns to an integrated circuit under test and a reference integrated circuit which is identical with the integrated circuit under test and is not in failure, measuring a difference between a current running through the integrated circuit under test and a current running through the reference integrated circuit, and judging whether the integrated circuit under test is in failure or not, based on a magnitude of spectrum component having a repetition frequency at which the test patterns are repeated.
Japanese Unexamined Patent Publication No. 11-94917 has suggested a method of testing a semiconductor device on which CMOS circuit is mounted, comprising the steps of inputting a clock signal into the semiconductor device, and calculating a maximum operating frequency on the basis of an inverse number of a delay time during which a power source current starts increasing at a clock operation timing and then becomes steadily equal to zero.
However, the above-mentioned methods are all accompanied with a problem that a reference, that is, data about a power source current of an integrated circuit having no failure has to be prepared in advance in order to test integrated circuits under test.
It is quite difficult to prepare such a reference. The reason is as follows. Data about a power source current is analog data, and is much influenced by processing conditions in fabrication of an integrated circuit. As a result, there is slight fluctuation among data about a power source current of integrated circuits having no failures. Hence, it is quite difficult to define a reference to be used for testing integrated circuits as to whether they are in failure or not.
In view of the above-mentioned problem, it is an object of the present invention to provide a method of detecting an integrated circuit in failure among integrated circuits, without preparing a reference, that is, data about a power source current of an integrated circuit having no failures, by utilizing data about a power source current of integrated circuits under test.
It is also an object of the present invention to provide an apparatus for doing the same.
Another object of the present invention is to provide a recording medium readable by a computer, storing a program therein for causing a computer to carry out the above-mentioned method or act as the above-mentioned apparatus.
In one aspect of the present invention, there is provided a method of detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the method including the steps of (a) assuming that all integrated circuits under test define a under-test integrated circuit set, and testing each one of the integrated circuits in the under-test integrated circuit set in a conventional manner, (b) removing integrated circuits having been judged to be in failure in the step (a), from the under-test integrated circuit set, (c) measuring spectrum of a current supplied from a power source into each one of the integrated circuits in the under-test integrated circuit set, (d) calculating both a mean value and standard deviation of the spectrum for the under-test integrated circuit set, (e) judging whether an integrated circuit is in failure or in no failure, based on both the mean value and the standard deviation of the spectrum, (f) removing integrated circuits having been judged to be in failure in the step (e), from the under-test integrated circuit set, and (g) judging the under-test integrated circuit set to be in no failure.
It is preferable that the method further includes the step (h) of normalizing the spectrum, the step (h) being to be carried out subsequently to the step (c).
It is preferable that the step (h) further includes the steps of (h1) summing up spectrum for all frequencies to have a total, and (h2) calculating a ratio of spectrum for each one of frequencies to the total.
It is preferable that the step (e) further includes the steps of (e1) calculating a gap between the spectrum and the mean value, (e2) dividing the gap by the standard deviation, (e3) comparing a quotient obtained in the step (e2) to a predetermined value, and (e4) judging an integrated circuit to be in failure, if the quotient is greater than the predetermined value, and judging an integrated circuit to be in no failure, if the quotient is equal to or smaller than the predetermined value.
There is further provided a method of detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the method including the steps of (a) assuming that all integrated circuits under test define a under-test integrated circuit set, and testing each one of the integrated circuits in the under-test integrated circuit set in a conventional manner, (b) removing integrated circuits having been judged to be in failure in the step (a), from the under-test integrated circuit set, (c) measuring spectrum of a current supplied from a power source into each one of the integrated circuits in the under-test integrated circuit set, (d) calculating a mean value and standard deviation of the spectrum for the under-test integrated circuit set, (e) checking whether the standard deviation is equal to or smaller than a predetermined value, (f) removing an integrated circuit having specific spectrum determined based on the mean value, from the under-test integrated circuit set, if the standard deviation is greater than the predetermined value, and repeating the steps (d), (e) and (f), and (g) judging the under-test integrated circuit set to be in no failure, if the standard deviation has been judged to be equal to or smaller than the predetermined value in the step (e).
It is preferable that the method further includes the step (h) of normalizing the spectrum, the step (h) being to be carried out subsequently to the step (c).
It is preferable that the step (h) further includes the steps of (h1) summing up spectrum for all frequencies to have a total, and (h2) calculating a ratio of spectrum for each one of frequencies to the total.
It is preferable that the step (f) further includes the steps of (f1) calculating a gap between the spectrum and the mean value for each one of frequencies, (f2) identifying an integrated circuit having a maximum gap among gaps calculated in the step (f1), and (f3) removing the integrated circuit identified in the step (f2), from the under-test integrated circuit set.
There is still further provided a method of detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the method including the steps of (a) testing integrated circuits to find an integrated circuit in no failure, (b) measuring spectrum of a current supplied from a power source into the integrated circuit, (c) judging the integrated circuit to be in failure, (d) repeating the steps (a) to (c) until spectrum is measured for N integrated circuits wherein N is a predetermined integer, (e) calculating a mean value and standard deviation for each frequencies with respect to the spectrum of the N integrated circuits, (f) judging whether the spectrum is abnormal or not, based on the mean value and the standard deviation, (g) deleting data of spectrum having been judged abnormal in the step (f), and repeating the steps (a) to (f), (h) defining the mean value and the standard deviation as a reference, (i) testing integrated circuits to find an integrated circuit in no failure, (j) measuring spectrum of a current supplied from a power source into the integrated circuit, (k) judging whether the spectrum is abnormal or not, based on the reference, and judging an integrated circuit to be either in no failure if the spectrum is abnormal or in failure if the spectrum is not abnormal, (l) carrying out the steps (i) to (j) for integrated circuits not tested yet, (m) defining integrated circuits having been judged to be in failure as integrated circuits not tested yet, and (n) repeating the steps (i) to (l).
It is preferable that the step (k) further includes the step of updating the reference, based on data of the spectrum.
It is preferable that the method further includes the step (o) of normalizing the spectrum, the step (o) being to be carried out subsequently to at least one of the steps (b) and (j).
It is preferable that the step (o) includes the steps of (o1) summing up spectrum for all frequencies to have a total, and (o2) calculating a ratio of spectrum for each one of frequencies to the total.
It is preferable that the method further includes the step (o) of normalizing the spectrum, the step (o) being to be carried out subsequently to at least one of the steps (b) and (j).
It is preferable that the step (o) includes the steps of (o1) summing up spectrum for all frequencies to have a total, and (o2) calculating a ratio of spectrum for each one of frequencies to the total.
It is preferable that the step (f) further includes the steps of (f1) calculating a gap between the spectrum and the mean value, (f2) dividing the gap by the standard deviation, (f3) comparing a quotient obtained in the step (f2) to a predetermined value, and (f4) judging the spectrum to be abnormal, if the quotient is greater than the predetermined value, and judging the spectrum not to be abnormal, if the quotient is equal to or smaller than the predetermined value.
It is preferable that the spectrum is judged not abnormal if the spectrum is equal to or smaller than the reference, and is judged abnormal if the spectrum is greater than the reference, in the step (k).
There is yet further provided a method of detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the method including the steps of (a) measuring spectrum of some of integrated circuits among integrated circuits under test, to thereby establish a reference, and (b) comparing the rest of integrated circuits among integrated circuits under test, to the reference to thereby judge whether each one of the rest of integrated circuits is in failure or not.
It is preferable that the method further includes the step of (c) judging whether the some of integrated circuits are in failure or not, based on the reference.
It is preferable that the method further includes the steps of (c) assuming that the some of integrated circuits are all in failure, and (d) judging again whether integrated circuits which have been judged to be in failure are in failure or not, after all integrated circuits have been judged as to whether they are in failure or not.
In another aspect of the present invention, there is provided an apparatus for detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the apparatus including (a) a tester which tests an integrated circuit in a conventional manner as to whether the integrated circuit is in failure or not, (b) a spectrum measurement unit which measures spectrum of the integrated circuit, (c) a first memory storing the spectrum therein, (d) a calculator calculating both a mean value and standard deviation of spectrum of all integrated circuits under test, based on the spectrum stored in the first memory, and (e) a controller which judges whether an integrated circuit is in failure or in no failure, based on both the mean value and the standard deviation of the spectrum.
It is preferable that the controller judges whether an integrated circuit is in failure or in no failure, based on comparison between a value defined as G/SD and a threshold value, wherein G indicates a gap between the spectrum and the mean value, and SD indicates the standard deviation.
It is preferable that the controller judges an integrated circuit to be in failure, if the value is greater than the threshold value, and judges an integrated circuit to be in no failure, if the value is equal to or smaller than the threshold value.
It is preferable that the apparatus further includes a second memory in which the threshold value is to be stored.
It is preferable that the controller judges that an integrated circuit having a maximum G/SD is in failure, when the standard deviation is greater than the threshold value.
It is preferable that the apparatus further includes a normalizer which normalizes the spectrum and replaces the previous spectrum with the normalized spectrum.
There is further provided an apparatus for detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the apparatus including (a) a tester which tests an integrated circuit in a conventional manner as to whether the integrated circuit is in failure or not, (b) a spectrum measurement unit which measures spectrum of the integrated circuit, (c) a first memory storing the spectrum therein, and (d) a controller which establishes a reference, based on spectrum of the predetermined number of integrated circuits under test, and judges whether an integrated circuit is in failure or in no failure, by comparing spectrum of each one of the integrated circuits under test to the reference.
It is preferable that the controller updates the reference, based on spectrum of an integrated circuit having been judged to be in no failure.
There is still further provided an apparatus for detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the apparatus including (a) a logic tester which tests an integrated circuit in a conventional manner as to whether the integrated circuit is in failure or not, (b) a spectrum measurement unit which measures spectrum of the integrated circuit, (c) a first memory storing the spectrum therein, (d) a calculator calculating both a mean value and standard deviation of spectrum of all integrated circuits under test, for each of frequencies, based on the spectrum stored in the first memory, and (e) a controller which judges whether an integrated circuit is in failure or in no failure, based on both the mean value and the standard deviation of the spectrum.
There is yet further provided an apparatus for detecting an integrated circuit in failure among integrated circuits, based on spectrum which is a result of analyzing a frequency of a current running through an integrated circuit when a test signal is applied to the integrated circuit, without preparing data of an integrated circuit in no failure, as a reference, the apparatus including (a) a logic tester which tests an integrated circuit in a conventional manner as to whether the integrated circuit is in failure or not, (b) a spectrum measurement unit which measures spectrum of the integrated circuit, (c) a first memory storing the spectrum therein, (d) a calculator calculating both a mean value and standard deviation of spectrum of all integrated circuits under test, for each of frequencies, based on the spectrum stored in the first memory, and (e) a controller which establishes a reference, based on spectrum of the predetermined number of integrated circuits under test, and judges whether an integrated circuit is in failure or in no failure, by comparing spectrum of each one of the integrated circuits under test to the reference.
It is preferable that the apparatus further includes (f) a first container for containing therein integrated circuits not tested yet, (g) a second container for containing therein integrated circuits having been judged to be in no failure, and (h) a third container for containing therein integrated circuits having been judged to be in failure.
It is preferable that the controller updates the reference, based on spectrum of an integrated circuit having been judged to be in no failure.
In still another aspect of the present invention, there is provided a recording medium readable by a computer, storing a program therein for causing a computer to carry out the above-mentioned method.
There is further provided a recording medium readable by a computer, storing a program therein for causing a computer to act as the above-mentioned apparatus.
The advantages obtained by the aforementioned present invention will be described hereinbelow.
As mentioned earlier, a method of detecting an integrated circuit in failure, based on spectrum of a power source current is accompanied with a problem that it is quite difficult to prepare a reference, that is, spectrum of a power source current of an integrated circuit having no failures, because of difference in processing conditions in fabrication of integrated circuits. The inventor found out the fact that almost all integrated circuits actually have no failures among integrated circuits having been judged to have no failures in accordance with a conventional method, and that quite a small number of integrated circuits having failures could not be detected in accordance with a conventional method. Based on this discovery, the inventor herein suggests a method of detecting an integrated circuit in failure by analyzing spectrum of a power source current of all integrated circuits under test.
Specifically, integrated circuits are all tested in accordance with a conventional method to thereby have an under-test integrated circuit set containing integrated circuits having been judged to have no failures in accordance with a conventional method. This under-test integrated circuit set contains integrated circuits which have failures, but have not been detected in accordance with a conventional manner, at a quite small rate, though.
Then, power source current spectrum is observed for each one of integrated circuits belonging to the under-test integrated circuit set, to thereby calculate a mean value and standard deviation. Then, a gap between spectrum and the mean value in each one of the integrated circuits is standardized by the standard deviation to thereby quantify the gap in the under-test integrated circuit set.
Though spectrum of integrated circuits having no failures are expected to distribute in the vicinity of the mean value, spectrum of integrated circuits having failures distribute much far away from the mean value. Accordingly, it would be possible to select integrated circuits having no failures by removing integrated circuits having spectrum distributing far away from the mean value, even without preparation of a reference, that is, data about spectrum of integrated circuits having no failures.
The above and other objects and advantageous features of the present invention will be made apparent from the following description made with reference to the accompanying drawings, in which like reference characters designate the same or similar parts throughout the drawings.